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1 features ? utilizes the arm7tdmi ? arm ? thumb ? processor core ? high-performance 32-bit risc architecture ? high-density 16-bit instruction set ? leader in mips/watt ? embedded ice (in-circuit emulation) 2k bytes (m63200) or 3k bytes (m43300) internal ram fully programmable external bus interface (ebi) ? maximum external address space of 64m bytes ? up to 8 chip selects ? software programmable 8/16-bit external data bus multi-processor interface (m63200 only) ? high-performance external processor interface ? 512 x 16-bit dual-port ram 8-channel peripheral data controller 8-level priority, individually maskable, vectored interrupt controller ? 5 external interrupts, including a high-priority, low-latency interrupt request 58 programmable i/o lines 6-channel 16-bit timer/counter ? 6 external clock inputs ? 2 multi-purpose i/o pins per channel 3 usarts ? 2 dedicated peripheral data controller (pdc) channels per usart ? support for up to 9-bit data transfers master/slave spi interface ? 2 dedicated peripheral data controller (pdc) channels ? 8- to 16-bit programmable data length ? 4 external slave chip selects programmable watchdog timer power management controller (pmc) ? cpu and peripherals can be deactivated individually ieee 1149.1 jtag boundary scan on all active pins fully static operation: 0 hz to 25 mhz (12 mhz @ 1.8v core, 25 mhz @ 2.7v core) 1.8v to 3.6v core operating voltage range 2.7v to 5.5v i/o operating voltage range -40 c to +85 c operating temperature range at91m63200 in a 176-lead tqfp package; at91m43300 in a 144-ball bga package description the at91m63200 and at91m43300 are members of the atmel at91 16/32-bit micro- controller family which is based on the arm7tdmi processor core. this processor has a high-performance 32-bit risc architecture with a high-density 16-bit instruction set and very low power consumption. in addition, a large number of internally banked registers result in very fast exception handling, making the device ideal for real-time control applications. the at91 arm-based mcu family also fea- tures atmel?s high-density, in-system programmable, nonvolatile memory technology. both products have a direct connection to off-chip memory, including flash, through the external bus interface. for the at91m63200, the multi-processor interface (mpi) provides a high-perfor- mance interface with an external coprocessor or a high bandwidth peripheral. both products are manufactured using atmel's high-density cmos technology. by combining the arm7tdmi microcontroller core with on-chip sram, a multi-processor interface and a wide range of peripheral functions on a monolithic chip, the at91m63200 and at91m43300 provide a highly-flexible and cost-effective solution to many compute-intensive real-time applications. at91 arm ? thumb ? microcontrollers at91m63200 at91m43300 electrical characteristics rev. 1090a?04/00
at91m6300/m43300 2 absolute maximum ratings* dc characteristics operating temperature (commercial) ........0 to +70 c *notice: stresses beyond those listed under ?absolute maxi- mum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. operating temperature (industrial) .....-40 c to +85 c voltage on any input pin with respect to ground.......................-0.5v to +5.5v maximum operating voltage (core) .....................3.6v maximum operating voltage (i/os) ......................5.5v dc output current ..............................................4 ma symbol parameter condition min typ max units v ddcore (1) 1. see table 4. dc supply voltage core 1.8 3.6 v v ddio dc supply i/os 2.7v = < v ddcore = < 3.6v v ddcore v ddcore + 2.0 or 5.5 v 1.8v = < v ddcore = < 2.7v 2.7 3.3 t a ambient temperature -40 85 c v il low-level input voltage -0.3 0.8 v v ih high-level input voltage 2 v ddio + 0.3 v v ol low-level output voltage 2.7 = < v ddio = < 3.6; i o (2) = 2 ma 2. i o = output current. 0.4 v v ddcore = < v ddio = < 5.5v; i o (2) = 4 ma 0.4 v v oh high-level output voltage 2.7 = < v ddio = < 3.6; i o (2) = 2 ma v ddio - 0.4 v v ddcore = < v ddio = < 5.5v; i o (2) = 4 ma v ddio - 0.4 v i leak input-leakage current 100 na i pull input pull-up current 100 a i cap input capacitance 12 pf i sc static current v ddio = v ddcore = 3.6v mcki = 0 hz, nrst = 1 60 a
at91m6300/m43300 3 power consumption the values in the following tables are measured values in the operating conditions indicated (i.e. v ddio = 3.3v, v ddcore = 3.3v or 1.8v; t = 25 ). they represent the power consumption on the v ddcore power supply. table 1. core power consumption mode conditions v ddcore unit 1.8v 3.3v reset 0.05 0.41 mw/mhz normal fetch in arm mode out of internal sram all peripheral clocks activated 3.1 13.3 fetch in arm mode out of internal sram all peripheral clocks deactivated 1.8 7.4 idle all peripheral clocks activated 2.0 8.7 all peripheral clocks deactivated 0.54 2.4 table 2. core power consumption per peripheral peripheral v ddcore unit 1.8v 3.3v pio controller 0.07 0.32 mw/mhz timer counter channel 0.07 0.28 timer counter block (3 channels) 0.18 0.75 usart 0.22 0.99 spi 0.22 1.02
at91m6300/m43300 4 conditions environment constraints the output delays are valid for a capacitive load of 50 pf as shown in figure 1. figure 1. output/bidir pad capacitive load timing results the output delays are for a capacitive load of 50 pf as shown in figure 1. in order to obtain the timing for other capacitance values, the following equation should be used. in the tables that follow, the output delays are for industrial conditions only. vo lt ag e rang es although the core may be supplied between 1.8v and 3.6v, there are two voltage ranges that have been characterized for timing purposes. these are from 1.8v to 2.2v (core @ 2v), and 2.7v to 3.6v (core at 3.3v). timing values are given for both sets of condi- tions, as in table 4. pa d c l = 50 pf tt datasheet factor c load 50 pf ? () + = table 3. derating factor due to capacitive load variation parameter commercial industrial units factor 0.052 0.058 ns/pf table 4. voltage ranges for timing characterization condition v ddcore v ddio unit minimum maximum minimum maximum core @ 2v 1.8 2.2 2.7 3.3 v core @ 3.3v 2.7 3.6 2.7 5.5
at91m6300/m43300 5 clock waveforms figure 2. clock waveform table 5. clock waveform parameters symbol parameter minimum maximum units core @2v core @3.3v core @2v core @3.3v 1/(t cp ) oscillator frequency 12 25 mhz t cp main clock period 83 40 ns t ch high time tbd 18 t cl low time tbd 18 t r rising edge tbd 7 t f falling edge tbd 7 table 6. clock propagation times symbol parameter minimum maximum units core @2v core @3.3v core @2v core @3.3v t cdlh rising edge propagation time tbd 20 tbd tbd ns t cdhl falling edge propagation time tbd 18 tbd tbd t ch t cl t cp mcki mcko t cdlh t cdhl 0.7 vddio 0.3 vddio t r t f
at91m6300/m43300 6 ac characteristics ebi signals relative to mcki the following tables show timings relative to operating condition limits defined in table 4. see figure 3. table 7. general purpose ebi signals symbol parameter minimum maximum units core @2vcore @3.3vcore @2vcore @3.3v ebi 1 mcki falling to nub valid tbd 20 ns ebi 2 mcki falling to nlb/a0 valid tbd 20 ns ebi 3 mcki falling to a7 - a1 valid tbd 20 ns ebi 4 mcki falling to a23 - a8 valid tbd 20 ns ebi 5 mcki falling to chip select tbd 5 tbd 20 ns ebi 6 nwait setup before mcki rising tbd 5 ns ebi 7 nwait hold after mcki rising tbd 4 ns table 8. ebi write signals symbol parameter minimum maximum units core @2vcore @3.3vcore @2vcore @3.3v ebi 8 mcki rising to nwr active (no wait states) tbd 20 ns ebi 9 mcki rising to nwr active (wait states) tbd 20 ns ebi 10 mcki falling to nwr inactive (no wait states) tbd 20 ns ebi 11 mcki rising to nwr inactive (wait states) tbd 20 ns ebi 12 mcki rising to d0 - d15 out valid tbd 20 ns ebi 19 nwr high to a23 - a1, nub/nlb/a0, ncs, cs changes (no wait states) tbd 2 ns ebi 20 nwr high to a23 - a1, ncs, cs changes (wait states) t cp/2 ns ebi 21 data out valid before nwr high t ch - 5 ns ebi 22 data out valid after nwr high t cp/2 ns
at91m6300/m43300 7 notes: 1. early read protocol 2. standard read protocol table 9. ebi read signals symbol parameter minimum maximum units core @2v core @3.3v core @2v core @3.3v ebi 13 mcki falling to nrd valid (1) tbd 5 tbd 18 ns ebi 14 mcki rising to nrd valid (2) tbd 20 ebi 15 d0 - d15 in setup before mcki falling tbd 0 ebi 16 d0 - d15 in hold after mcki falling tbd 3 ebi 17 nrd high to a23 - a1, ncs, cs changes tbd 0 ebi 18 data hold after nrd high tbd 0
at91m6300/m43300 8 figure 3. ebi signals relative to mcki notes: 1. early read protocol 2. standard read protocol ncs a1 - a23 nrd (1) d0 - d15 read mcki nub/nlb/a0 nrd (2) nwait nwr (no wait states) d0 - d15 to write nwr (wait states) no wait wait ebi 1 /ebi 2 ebi 3 /ebi 4 ebi 5 ebi 6 ebi 7 ebi 8 ebi 10 ebi 9 ebi 11 ebi 12 ebi 13 ebi 14 ebi 15 ebi 16 cs ebi 13 ebi 5 no wait wait ebi 17 ebi 18 ebi 19 ebi 21 ebi 22 ebi 20 ebi 22
at91m6300/m43300 9 peripheral signals relative to mcki usart signals the inputs can be used synchronously or asynchronously (in relation to mcki). for synchronous and asynchronous usart inputs, certain setup/hold constraints must be met. these constraints are shown in tables 11 and 12 and are represented in figure 4. for asynchronous inputs, a minimum pulse-width is necessary as shown in table 13 and as represented in figure 4. table 10. usart outputs symbol parameter minimum maximum units core @2vcore @3.3vcore @2vcore @3.3v us 1 mcki rising to sck output rising/falling tbd tbd tbd 25 ns us 2 mcki rising to txd toggling tbd tbd tbd 35 ns us 3 sck output falling to txd toggling tbd tbd tbd 10 ns us 4 sck input falling to txd toggling tbd tbd tbd 2(t cp ) + 35 ns table 11. usart synchronous input setup/hold constraints symbol type of input parameter setup hold units us 5 synchronous rxd toggling relative to mcki falling 0 5 ns us 6 synchronous sck input rising relative to mcki rising 0 5 ns us 7 synchronous sck input falling relative to mcki rising 0 5 ns table 12. usart asynchronous input setup/hold constraints symbol type of input parameter setup hold units us 8 asynchronous rxd toggling relative to sck input rising t cp/2 - 2 t cp/2 + 2 ns table 13. usart asynchronous input minimum pulse-width symbol type of input parameter pulse-width units us 9 asynchronous rxd/sck minimum pulse-width 3(t cp /2) ns
at91m6300/m43300 10 figure 4. usart signals relative to mcki sck output mcki sck input txd rxd us 5s us 5h us 2 us 1 us 3 us 1 us 4 us 6h us 7h us 8s us 6s us 7s us 8h rxd/sck (asynchronous) us 9
at91m6300/m43300 11 spi signals figure 5. spi signals table 14. spi signals in master mode symbol parameter minimum maximum units core @2v core @3.3v core @2v core @3.3v t spck spi operating period 4(t cp ) 16320(t cp )ns f spck spi operating frequency 1/16320(t cp )1/4(t cp )ghz sp 1 delay before npcs[3:0] 4(t cp ) 261120(t cp )ns sp 2 delay between chip selects 6(t cp ) 8160(t cp )ns sp 3 delay before spck 2(t cp ) 8160(t cp )ns sp 4 miso/spck setup time tbd 18 ns sp 5 miso/spck hold time tbd 0 ns sp 6 mosi valid after spck edge tbd 7 ns sp 1 sp 2 sp 3 t spck sp 4 sp 5 sp 6 msb in data lsb in msb out data lsb out npcs[3:0] output spck output cpol = 0 spck output cpol = 1 miso input mosi output
at91m6300/m43300 12 timer counter signals due to internal synchronization of input signals, there is a delay between an input event and a corresponding output event. this delay is 3(t cp ) in waveform event detection mode and 4(t cp ) in waveform total-count detection mode. in addition there are the following delays relative to mcki waveforms. the inputs can be used synchronously or asynchronously (in relation to mcki). for synchronous timer inputs, certain setup/hold constraints must be met. these constraints are shown in the table 16 and are represented in figure 6. for asynchronous inputs, a minimum pulse-width and a minimum input period are necessary as shown in tables 17 and 18 and as represented in figure 6. table 15. timer outputs symbol parameter maximum units core @2v core @3.3v tc 1 mcki rising to tioa rising tbd 22 ns tc 2 mcki rising to tioa falling tbd 22 tc 3 mcki rising to tiob rising tbd 22 tc 4 mcki rising to tiob falling tbd 22 table 16. synchronous timer inputs symbol type of input parameter setup hold units core @2v core @3.3v core @2v core @3.3v tc 5 synchronous tioa/tiob rising relative to mcki rising tbd 2 tbd 5 ns tc 6 synchronous tioa/tiob falling relative to mcki rising tbd 2 tbd 5 tc 7 synchronous tclk rising relative to mcki rising tbd 2 tbd 5 tc 8 synchronous tclk falling relative to mcki rising tbd 2 tbd 5 table 17. asynchronous timer input minimum pulse-width symbol type of inputs parameter pulse-width units tc 9 asynchronous tclk/tioa/tiob minimum pulse-width 3(t cp /2) ns table 18. asynchronous timer input minimum input period symbol type of inputs parameter input period units tc 10 asynchronous tclk/tioa/tiob minimum input period 5(t cp /2) ns
at91m6300/m43300 13 figure 6. timer relative to mcki tc 1 tc 2 tc 3 tc 4 mcki tioa/tiob/tclk asynchronous in tclk synchronous input tioa/tiob synchronous inputs tioa output tiob output tc 5h tc 5s tc 6s tc 6h tc 7h tc 7s tc 8h tc 8s tc 9 3(t cp /2) 1(t cp ) detect detect tc 10
at91m6300/m43300 14 watchdog timer signals figure 7. watchdog signals relative to mcki reset signals certain setup constraints must be met. these constraints are shown in table 20 and are represented in figure 8. a minimum pulse width is necessary as shown in table 21 and as represented in figure 8. figure 8. reset signals relative to mcki only the nrst rising edge is synchronized. the falling edge is asynchronous. table 19. watchdog timer outputs symbol parameter maximum units core @2v core @3.3v wd 1 mcki rising to nwdovf rising tbd 20 ns wd 2 mcki rising to nwdovf falling tbd 20 mcki nwdovf output wd 1 wd 2 zz table 20. reset setup constraints symbol parameter setup units core @ 2v core @3.3v rst 1 nrst rising related to mcki rising tbd 5 ns table 21. reset minimum pulse-width symbol parameter pulse-width units rst 3 nrst minimum pulse-width 10(t cp )ns mcki nrst rst 1h rst 1s rst 3
at91m6300/m43300 15 advanced interrupt controller signals the inputs can be used synchronously or asynchronously (in relation to mcki). for synchronous aic inputs, certain setup/hold constraints must be met. these constraints are shown in table 22 and are represented in figure 9. for asynchronous inputs, a minimum pulse width is necessary as shown in table 23 and as represented in figure 9. figure 9. aic signals relative to mcki table 22. aic synchronous input setup/hold constraints symbol type parameter setup hold units core @ 2v core @3.3v core @ 2v core @3.3v aic 1 synchronous fiq/irq0/irq1/irq2/irq3 rising relative to mcki rising tbd0tbd4 ns aic 2 synchronous fiq/irq0/irq1/irq2/irq3 falling related to mcki rising tbd0tbd4 ns table 23. aic asynchronous input minimum pulse-width symbol type parameter pulse-width units aic 5 asynchronous fiq/irq0/irq1/irq2/irq3 minimum pulse-width 3(t cp /2) ns table 24. aic asynchronous input minimum input period symbol type parameter input period units aic 6 asynchronous aic minimum input period 5(t cp /2) ns mcki aic 1h fiq/irq0/irq1/irq2/irq3 synchronous input fiq/irq0/irq1/irq2/irq3 asynchronous input aic 1s aic 2h aic 1s aic 5 aic 6
at91m6300/m43300 16 parallel i/o signals the inputs can be used synchronously or asynchronously (in relation to mcki). for synchronous pio inputs, certain setup/hold constraints must be met. these constraints are shown in the table 26 and are represented in figure 10. for asynchronous inputs, a minimum pulse width is necessary as shown in table 27 and as represented in figure 10. figure 10. pio signals relative to mcki table 25. pio outputs symbol parameter maximum units core @2v core @3.3v pio 1 mcki falling to pio output rising tbd 22 ns pio 2 mcki falling to pio output falling tbd 22 ns table 26. pio synchronous input setup/hold constraints symbol type parameter setup hold units core @ 2v core @3.3v core @ 2v core @3.3v pio 3 synchronous pio input rising related to mcki rising tbd 2 tbd 5 pio 4 synchronous pio input falling related to mcki rising tbd 2 tbd 5 ns table 27. pio asynchronous input minimum pulse-width symbol type parameter pulse-width units pio 5 asynchronous pio input minimum pulse-width 3(t cp /2) ns mcki pio synchronous inputs pio asynchronous inputs pio outputs pio 1 pio 2 pio 3h pio 3s pio 4h pio 4s pio 5
at91m6300/m43300 17 multi-processor interface signals (at91m63200 only) figure 11. external arbitration data transfer mpi_br mpi_bg t2 mpi_d[15:0] t 1 table 28. external arbitration symbol parameter minimum maximum units core @2v core @3.3v core @2v core @3.3v t 1 mpi_br high to mpi_bg high delay (30 pf) t cp 2 x t cp + 12 ns t 2 mpi_br low to mpi_bg low tbd 12
at91m6300/m43300 18 figure 12. mpi read access table 29. mpi read access symbol parameter minimum maximum units core @2v core @3.3v core @2v core @3.3v t rc read cycle time tbd 22 ns t aa address access time tbd 22 ns t acs chip select access time tbd 22 ns t oe output enable to output valid tbd 10 ns t lb, t ub byte select to output valid tbd 10 ns t oh output hold from address change tbd 0 ns t clz chip select to output in low-z tbd 0 ns t olz output enable to output in low-z tbd 0 ns t lblz, t ublz byte select to output in low-z tbd 0 ns t chz chip deselect to output in high-z tbd 7 ns t ohz output disable to output in high-z tbd 7 ns t lbhz, t ubhz byte deselect to output in high-z tbd 7 ns mpi_a[9:1] mpi_ncs mpi_d[15:0] high impedance valid data mpi_noe mpi_nlb, mpi_nub valid address t rc t oh t chz t ohz t lbhz t aa t acs t ubhz t ub t lb t oe t olz t lblz t ublz t clz
at91m6300/m43300 19 figure 13. mpi write access (mpi_rnw controlled) table 30. mpi write access symbol parameter minimum maximum unit core @2v core @3.3v core @2v core @3.3v t wc write cycle time tbd 10 ns t aw address valid to end of write tbd 10 ns t cw chip select to end of write tbd 10 ns t wp write pulse-width tbd 10 ns t lbw, t ubw byte select to end of write tbd 10 ns t as address setup time tbd 0 ns t wr write recovery time tbd 0 ns t dw data valid to end of write tbd 10 ns t dh data hold time from end of write tbd 0 ns t ow write disable to output in low-z tbd 10 ns t whz write enable to output in high-z tbd 7 ns mpi_a[9:1] mpi_rnw valid data valid address high-z high-z high-z mpi_ncs mpi_nlb, mpi_nub mpi_dout[15:0] mpi_din[15:0] t wc t aw t as t wr t wp t cw t lbw t ubw t whz t ow t dh t dw
at91m6300/m43300 20 figure 14. mpi write access (mpi_ncs controlled) figure 15. mpi write access (mpi_nlb, mpi_nub controlled) mpi_a[9:1] mpi_rnw valid data valid address high-z high-z mpi_ncs mpi_nlb, mpi_nub mpi_din[15:0] t wc t aw t as t wr t wp t cw t lbw t ubw t dh t dw mpi_a[9:1] mpi_rnw valid data valid address high-z high-z mpi_ncs mpi_nlb, mpi_nub mpi_din[15:0] t wc t aw t as t wr t wp t lbw t ubw t dh t dw t cw
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